COMMENT ⊗   VALID 00014 PAGES
C REC  PAGE   DESCRIPTION
C00001 00001
C00002 00002	Information about the KL10, KA10, and 166.
C00006 00003	CONO APR,	166		KA			KL
C00009 00004		166			KA			KL
C00012 00005	KL10 new instructions:
C00019 00006	DTE20 KL10 I/O Functions
C00022 00007	Clocks and meters
C00028 00008	Performance Analysis
C00032 00009	KL10 to PDP-11 command word formats.
C00038 00010	KL10 UPT/EPT Special Locations
C00040 00011	Monitor Programming
C00043 00012		KL10 Folklore (from MIT)
C00047 00013	User programming differences between the KL10 and the KA10.
C00060 00014	Reloading the KL10
C00065 ENDMK
C⊗;
Information about the KL10, KA10, and 166.

This document is intended as quick reference summary for programming
the various processors.  An attempt has been made to make the
information reported here accurate and complete.  The primary sources
of information from this was made are the KL10 prints and the source
files for KLDCP.  The status of existing modifications to the KA10
and 166 are reported to the extent that those modifications can be
determined.



		166			KA			KL	
CONO PI,

18	unused			Clr Power Fail		Write even address parity
19	unused			Clr Parity Error	Write even data parity
20	Clr Parity Error	Dis Parity Error Int	Write even directory parity
21	Dis Parity Error Int	Enb Parity Error Int	unused
22	Enb Parity Error Int	Set CPA MEM PROT 	Drop prog requests on sel chan
23	Clear PI system
24	Request int on sel chn				[Interrupts requested by
25	Turn on sel chn					this function (Bit 24) can
26	Turn off sel chn				be dropped only by use of
27	Turn off PI system				bit 22.]
28	Turn on PI system
29	Select channel 1
30	Select channel 2
31	Select channel 3
32	Select channel 4
33	Select channel 5
34	Select channel 6
35	Select channel 7


CONI PI,

 0	unused			unused			unused
...
10	unused			unused			unused
11	unused			unused			Prog request on channel 1
12	unused			unused			Prog request on channel 2
13	unused			unused			Prog request on channel 3
14	unused			unused			Prog request on channel 4
15	unused			unused			Prog request on channel 5
16	unused			unused			Prog request on channel 6
17	unused			unused			Prog request on channel 7
18	unused			Power fail		Write even address parity
19	unused			Parity error		Write even data parity
20	Parity error		Parity Int Enb		Write even directory parity
21	In progress on chn 1
22	In progress on chn 2
23	In progress on chn 3
24	In progress on chn 4
25	In progress on chn 5
26	In progress on chn 6
27	In progress on chn 7
28	PI system on
29	Channel active 1
30	Channel active 2
31	Channel active 3
32	Channel active 4
33	Channel active 5
34	Channel active 6
35	Channel active 7



CONO APR,	166		KA			KL

18	Clr PDLOV		unused			unused
19	Clr IOT user		IOB reset		IOB reset
20	Clr CONS flg		unused			Enb flgs selected by b24:31
21	unused			Clr Addr Brk flg	Dis flgs selected by b24:31
22	Clr MPV			Clr MPV			Clr flgs selected by b24:31
23	Clr NXM			Clr NXM			Set flgs selected by b24:31
24	Dis CLK Int		Dis CLK Int 		SBUS error
25	Enb CLK Int		Enb CLK Int		NXM error
26	Clr CLK flg		Clr CLK flg		In-Out Page Fail
27	Dis PC chg Int		Dis FOV Int		MB parity error
28	Enb PC chg Int		Enb FOV Int		Cache directory error
29	Clr PC chg flg		Clr FOV flg		Cache address parity error
30	Dis AROV Int		Dis AROV Int		Power fail
31	Enb AROV Int		Enb AROV Int		Sweep done
32	Clr AROV flg		Clr AROV flg		unused
33	APR PIA 4
34	APR PIA 2
35	APR PIA 1


CONI APR,

 0	unused			unused			unused
...
 5	unused			unused			unused
 6	unused			unused			SBUS error enb
 7	unused			unused			NXM error enb
 8	unused			unused			In-Out Page fail enb
 9	unused			unused			MB parity error enb
10	unused			unused			Cache directory error enb
11	unused			unused			Cache addr parity error enb
12	unused			unused			Power Fail enb
13	unused			unused			Sweep Done enb
14	unused			unused			unused
...
18	CONS flg		unused			unused
19	PDLOV			PDLOV			Sweep Busy
20	User IOT mode		User IOT mode		unused
21	User Mode		Address Break		unused
22	MPV flg			MPV flg			unused
23	NXM flg			NXM flg			unused
24	unused			unused			SBUS error flg
25	CLK enb			CLK enb			NXM error flg
26	CLK flg			CLK flg			In-Out page fail flg
27	unused			¬CPA INT		MB parity error flg
28	PC CHG enb		FOV enb			Cache directory error flg
29	PC CHG flg		FOV flg			Cache addr parity error flg
30	unused			MA Trap offset		Power fail flg
31	AROV enb		AROV enb		Sweep done flg
32	AROV flg		AROV flg		Int requested flg
33	APR PIA 4
34	APR PIA 2
35	APR PIA 1


	166			KA			KL
PC and flags

 0	AR OV						[See note]
 1	AR CRY0						
 2	AR CRY1
 3	PC Change		FOV
 4	BIS						First Part Done
 5	User
 6	User In-Out
 7	unused			unused			Public
 8	unused			unused			Address Failure Inhibit
 9	unused			unused			Trap 2
10	unused			unused			Trap 1
11	unused			FXU
12	unused			DCK
13-17	Zero
18-35	PC

[Note: Bit 0 of the PC represents SCD PCP in exec mode, except in JFCL 10,
which tests AROV.  SCD PCP is loaded from bit 0 of a PC word restored by
JRST 2, (or from a UUO or trap new PC word). PCP means previous context
public, i.e., supervisor was called from a public, not a concealed, program.]

KA10 special features:
	CONI PTP, bit 28 = KEY NXM STOP
	CONI TTY, bit 28 = 1 (for processor identification)
	Device OAP (Other Arithmetic Processor, Device code = 20)
		CONO OAP, bit 28 clear IPI APR flag
			  bit 29 set other processor's IPI APR flag
		CONI OAP, bit 28 IPI APR flag
			  bit 29 Other processor's IPI APR flag
		IPI APR flag requests an interrupt on the APR channel

Known differences between the Stanford A.I. Lab KA10 and standard KA10's.

1.	FIX (opcode 247)
	Used to make a floating point number fixed point.

2.	PUSHJ doesn't clear BIS

3.	Memory Subroutines in the processor have been speeded up.

4.	Key NXM stop appears in the CONI PTP,

5.	Permanent IOB Drum Split

6.	JRST 10, and JRST 4, are illegal in User IOT mode

7.	CONO PI,<set MPV>

8.	BBN pager, etc.


166 special features:
	CONI TTY, bit 27 = 1 (for processor identification)
	IBP AC, loads the AC with the incremented byte pointer


KL10 new instructions:

APRID	BLKI	APR,		read APR serial, options, microcode version

	BLKO	APR,		load cache refill algorithm RAM
Writes into a 128x3 table.  One BLKO per 3 bit entry.
			Effective address of the instruction decodes as follows:
			Bit
			18	Data bit 4   New order bit
			19	Data bit 2   New LRU 2
			20	Data bit 1   New LRU 1
			21:26	unused
			27	RAM address 64   (From new MRU 2)
			28	RAM address 32   (From new MRU 1)
			29	RAM address 16   (From old MRU 2)
			30	RAM address  8   (From old MRU 1)
			31	RAM address  4	 (From old order bit)
			32	RAM address  2   (From old LRU 2)
			33	RAM address  1   (From old LRU 1)
			34:35	unused

Each (quadruple of) cache line(s) has a 5 bit field (Cache Use Bits)
to specify which of the caches was LRU, MRU and the relative order of
the other two caches.  These five bits plus 2 bits of new MRU (i.e.,
the currently referenced cache) are used to index a 128 word table to
produce 3 bits of LRU and order which together with the 2 bits of new
MRU replace the 5 Cache Use bits.


	DATAO	APR,		set state of address comp address/condition
			Bit
			 9	Inst Fetch
			10	Data Fetch
			11	Write
			12	(0=exec, 1=user)
			13-35	VMA

	DATAI	APR,		read state of address compare conditions
					(Only bits 9-12, as in DATAO APR,)
			[Address break appears to cause a page fault]

RDERA	BLKI	PI,		read error address register
	BLKO	PI,		SBUS diagnostic
	DATAO	PI,		unused
	DATAI	PI,		unused

(PAG is device 10)
	DATAO	PAG,		Set User Context
			Bit
			 0	Load AC blocks from bits 6-11
			 1	Load previous context from bits 12-17
			 2	Load UBR, and look at bit 18.
				After storing accounting meters in old
				UBR (or if bit 18 is a 1, without storing
				accounting meters) clear accounting meters.
			 3-5	unused
			 6-8	Current AC block number
			 9-11	Previous AC block number
			12	CWSX (if enabled by bit 1)
			13-17	Previous section (if enabled by bit 1)
			18	Inhibit storing accounting meters
				If bit 2 is a 1 and bit 18 is zero,
				store current accounting meters in current
				UBR.  
			19-23	unused
			24-35	User base
	DATAI	PAG,		Read User context
	BLKO	PAG,E		Invalidate page table entry corresponding
				to the (8) page(s) addressed by (E⊗-9)&770
	BLKI	PAG,		unused
	CONO	PAG,		Set Exec context, cache control, trap enb
			Bit
			18	Cache Look
			19	Cache Load
			20	unused
			21	KL10 paging
			22	Trap and Map Enable
			23-35	Exec Base register
	CONI	PAG,		Read exec context (same as CONO PAG,)

A CONO PAG, (or a DATAO PAG, with Bit 0 a 1) will invalidate the entire
paging ram.

A UUO stores the
Process context word (UPT location 426)
60wxyz,,ubr
w=current ac block
x=previous ac block
yz=cwsx and previous section


(CCA is device 14)
SWPIA	DATAI	CCA,			Sweep Cache, invalidate all
SWPVA	BLKO	CCA,			Sweep Cache, validate core
SWPUA	DATAO	CCA,			Sweep Cache, validate core, invalidate cache
SWPIO	CONI	CCA,			Sweep Cache, invalidate one page.
					b23:35 are the physical page to sweep
SWPVO	CONSZ	CCA,			Sweep Cache, validate one page in core
SWPUO	CONSO	CCA,			Sweep Cache, validate one page in core,
						invalidate one page in cache
	BLKI	CCA,			unused?
	CONO	CCA,			unused?

ADJBP	IBP	AC,			if AC field is zero, this is IBP; if AC
					is non zero, C(AC) is the byte pointer
					adjustment, i.e., the number of times to
					increment (decrement) the byte pointer.
					Resulting byte pointer is stored in AC.
					Unlike IBP, ADJBP maintains the same
					alignment of bytes in the word as in the
					original byte pointer, e.g., 
					IBP 000700,,1000 → 350700,,1001
					whereas adjusting by 1 the same pointer
					produces 340700,,1001
					
DADD					C(AC,AC+1)+C(E,E+1) → C(AC,AC+1)
DSUB					C(AC,AC+1)-C(E,E+1) → C(AC,AC+1)
DMUL					C(AC,AC+1)*C(E,E+1) → C(AC,AC+1,AC+2,AC+3)
DDIV					C(AC,AC+1,AC+2,AC+3)/C(E,E+1) →
					 C(AC,AC+1) quotient, C(AC+2,AC+3) remainder
ADJSP	AC,E				C(AC)+E,,E → C(AC).  Carry out of bit 18
					is inhibited.  (Note this is immediate mode)
MAP	

Other differences
	In BLT the KL10 always stores in AC the updated BLT pointer, which
will contain <one beyond source>,,<one beyond destination>.



DTE20 KL10 I/O Functions

CONO DTE0,

18:21		unused
22		DONG11	KL10 requests service by the 11
23		clear RELOAD PDP11 button
24		set RELOAD PDP11 button
25		unused
26		Clear DONG10	PDP-10 has responded to interrupt from 11
27		unused
28		unused
29		clear TO-11 Normal Termination and TO-11 Error Termination
30		clear TO-10 Normal Termination and TO-10 Error Termination.
31		enable loading bits 32:35
32		Set PI0 ENABLE (if enabled by bit 31) 
			[This is ignored on a privileged 11]
33:35		PIA


CONI DTE0,	[Bits marked with * request interrupts]

00:19		unused
20		1 if this DTE is restricted, 0 if privileged.
21		PDP-11 Power failure
22		DONG11	KL10 requests service by the 11
23		unused
24		unused
25		unused
26		*DONG10	PDP-11 requests an interrupt on the KL10
27		*TO-11 Error Termination
28		unused
29		*TO-11 Normal Termination
30		*TO-10 Normal Termination
31		*TO-10 Error Termination
32		PI0 Enable
33:35		PIA 4,2,1 (1)

 
DATAI DTE0,	unassigned. Makes EBUS parity errors.

DATAO DTE0,E

00:22		unused
23		bit → TO-10 I BIT
24:35		bits → EBHOLD 11-00
		[Bit 23 a zero means that when the TO-10 transfer completes,
		only the 10 (not the 11) will be interrupted.  This
		permits scatter read under control of the 10]
		[Bits 24:35 are a negative byte count of the number of bytes
		to transfer before giving a normal termination interrupt.
		0 means transfer 0 bytes.]

Clocks and meters

There are 5 "clocks", each is actually a counter of some kind:

Interval		100 KHz			12 bits	EPT 514 (vector)
Time base		1 MHz rate		52 bits	EPT 510-511
Performance					52 bits	EPT 512-513
EBOX cycle count	1/2 EBOX clock rate	52 bits	UPT 504-505
MBOX cycle count	1 per EBOX mem req.	52 bits	UPT 506-507

The MBOX clock counter and EBOX clock counter are together referred to as
the "Accounting Meters."  All 52 bit clocks actually are double words in
in memory with 16 bits of each counter implemented in hardware too.
The 52 bit clocks are read with DATAI or BLKI which produce a double word
result suitable for DADD etc.  The low 12 bits of the low order counter
words are zero (in the hopes that a faster, compatible format clock
will be available on future machines).

MTR is 24, TIM is 20.

CONO MTR,	Accounting and Timebase Control, Interval Timer PIA

18		Enable bits 21:23
19		unused
20		unused
21		PI Acct Enable
22		Exec Acct Enable
23		Acct On
24		Turn off timebase
25		Turn on timebase
26		Clear Timebase
27		unused
28		unused
29		unused
30		unused
31		unused
32		unused
33		Interval timer PIA 4 
34		Interval timer PIA 2
35		Interval timer PIA 1

The accounting meters are enabled by:
	(Acct On) ∧
	(User ∨ ¬PI in progress ∨ PI Acct Enable) ∧
	(User ∨ PI in prog ∨ Exec Acct Enb)

When turned on, the accounting meters are enabled to count in user
mode, regardless of PI level.  Also, if Exec Acct Enb is true, meters
are enabled at UUO level (exec mode not PI in progress).  Also, if PI
Acct Enable is true, meters are enabled while PI in progress.  The
meters are disabled by either PI cycle or Ucode State 3.

When enabled, the MBOX meter counts when the MBOX finishes a
memory cycle requsted by the EBOX.  When enabled, the EBOX meter
counts every second MBOX clock tick unless the EBOX is waiting for
the MBOX.

CONI MTR,

0:17		Unused
18		unused
19		unused
20		unused
21		PI Acct Enable
22		Exec Acct Enable
23		Acct on
24		unused
25		Timebase on
26		unused
27		unused
28		unused
29		unused
30		unused
31		unused
32		unused
33		Interval meter PIA 4
34		Interval meter PIA 2
35		Interval meter PIA 1

CONO TIM,

18		Clear Up Counter
19		unused
20		unused
21		1=Turn on, 0=turn off interval timer
22		Clear Interval Done and Interval Overflow
23		Unused
24:35		Load Period Register

CONI TIM,

0:5		Unused
6:17		Up counter
18:20		unused
21		Interval Timer On
22		*Interval Timer Done
23		*Interval Overflow
24:35		Period register
		[When the Up Counter reaches the value specified in
		the period register, it sets Interval Timer Done
		and resets the up counter to zero.
		Interval timer interrupts execute location 514 in the EPT.
		If you set a period that's smaller than the current
		value of the Up Counter,  Up Counter Overflow will
		be set (after the up counter reaches maximum value).]


Timebase

DATAI TIM,	[read doubleword timebase]


Accounting meters

DATAI MTR,	[read doubleword EBOX meter]
BLKI MTR,	[read doubleword MBOX meter]

seconds of KL10 time = EBOX/12,500,000 + MBOX*<avg. memory cycle time>

DATAO PAG, with bit 2 set will reset the UBR.  Unless bit 18 is set
to inhibit storing accounting meters (useful if there's no old UPT),
the old EBOX and MBOX counters are added to the old UPT 504-507.  The
meters are cleared.

DATAO	TIM,	[unused]
Performance Analysis

BLKO TIM,	set performance counter enables

 0		Internal Channel 0 Busy Enb			A
 1		Internal Channel 1 Busy Enb			A
 2		Internal Channel 2 Busy Enb			A
 3		Internal Channel 3 Busy Enb			A
 4		Internal Channel 4 Busy Enb			A
 5		Internal Channel 5 Busy Enb			A
 6		Internal Channel 6 Busy Enb			A
 7		Internal Channel 7 Busy Enb			A
 8		Internal Channel Don't Care			A
 9		Microcode State Don't Care 			B
10		ECL probe low PA enb				C
11		ECL probe don't care				C
12		¬Cache Request Enb				D
13		¬Cache Fill (miss) Enb				D
14		¬Cache (Ebox) writeback Enb			D
15		¬Cache Sweep Enb				D
16		Cache don't care				D
17		unused
18		PI 0 PA enb					E
19		PI 1 PA enb					E
20		PI 2 PA enb					E
21		PI 3 PA enb					E
22		PI 4 PA enb					E
23		PI 5 PA enb					E
24		PI 6 PA enb					E
25		PI 7 PA enb					E
26		No PI PA enb					E
27		User PA enb					F
28		Mode PA don't care				F
29		1=event mode; 0=Duration mode
30		clear perf meter
31		Unused
32		Unused
33		unused
34		unused
35		unused

BLKI TIM,	read doubleword performance analysis counter

A Boolean condition consisting of the AND of six terms is formed.
In duration mode, while this condition is true, the performance meter
is counted at half the MBOX clock rate.  In event mode, every transition
of this condition from False to True is counted.  The condition is the
AND of six terms (designated A, B, C, D, E and F, to correspond to
the description of BLKO TIM, above).

A:	((Internal Channel n Busy)∧(Internal channel n Busy Enb)) ∨
		(Internal channel don't care)

B:	(Microcode state 01) ∨ (Microcode state don't care)

C:	((ECL probe state low enb)≠(Probe)) ∨ (ECL Probe don't care)

D:	((Fill cache read) ∧ (Cache fill enb)) ∨
	((EBOX waiting) ∧ (cache request enb)) ∨
	((EBOX writeback) ∧ (EBOX writeback enb)) ∨
	((Sweep writeback) ∧ (sweep writeback enb)) ∨
	(Cache don't care)

E:	((PI n is highest channel held or cycling) ∧ (PI n PA enb))  ∨
	((No PI channel is held)∧(No PI PA enb))

F:	((User mode)≡(User PA enb)) ∨ (Mode PA don't care)

DATAO MTR,	unused
BLKO MTR,	unused
KL10 to PDP-11 command word formats.

(CTY Typeout, etc)

The command word, $DTCMD (EPT location 451), has the following signifigance.
Bits 24:27 are the command type.  Bits 28:35 are the command argument.

Command type:

00	0000		CTY output.   Bits 29:35 are the character.

01	0400		Program Control.  Bits 32:35 specify subfunction:
				00	PDP-10 halted
				01	FATAL error
				02	Error halt
				03	End of Program
				04	End of Pass
				05	Read the clock default word to $DTF11.
					BYTE(4)CCHENB(26)0(3)CLKS,CLKR
					CCHENB = cache enables:
						10 - cache 0
						04 - cache 1
						02 - cache 2
						01 - cache 3
					CLKS = clock source
					CLKR = clock rate

				06	DIAMON file selection
				07	DIAMON file read
				10	PDP-10 program command to 11
				11:17	unused.

02	1000		Clock.  Bits 34:35 decode as follows:
				0	Disable.  TENCLK←0;
				1	Enable.   TENCLK←-1;
					Wait for clock to tick;  CLKCNT←0;
				2	Enable and wait.
					TENCLK←-400; C10CW←$DTT11;
					Wait for clock to tick; CLKCNT←0;
				3	Read PDP-10 Clock count.  $DTF11←CLKCNT;
				When the clock ticks and TENCLK≠0, CLKCNT is
				incremented, then if TENCLK=-1 or 
				(TENCLK=-400 and the low word of CLKCNT = C10CW)
				then $DTCLK←-1 and a 10 interrupt is requested
				via the DTE20.
				[The following are Stanford additions:]
				4	Set time base.  TIMBAS←@DTT11;
				5	Read time base. @DTT11←TIMBAS;
				[The timebase is a 47 bit count of 60ths.
				The origin is whatever you want (70,000 years).
				Reading and setting the timebase use a double word
				integer pointed to by DTT11 (the address is always
				a to-11 argument).]

03	1400		Read switches into $DTF11.
				The switches are simulated in PDP-11 hardware
				and software.  PDP-11 switches 15:00 correspond
				to bits 0:15 in the PDP-10 switches.  The remainder
				are set by the SW command in KLDCP
				0	Read Switch
				1	Read Switch, Enable auto deposit into DTSWR
				2	Read Switch, Disable auto deposit

04	2000		CTY output.   Same as function 0

05	2400		CTY input.
				This function appears to wait for all output to
				finish and then wait for a complete line to be
				typed before returning any non-null characters to
				the 10.  The 10 won't hang because of various
				timeouts.  Line editing would seem to be handled
				by the 11.

06	3000		Print Control.  Bits 28:35 are stored in $FORCE in KLDCP
				If $FORCE≠0 then force typeout despite ↑O,
				despite pdp-11 switches, despite selection of LPT.

07	3400		DDT mode input.  Character returned in $DTF11.
				A null is returned in case of timeout.
				Force all typeout.  Return (on a character, not
				a line basis) the characters as they're typed.

10	4000		Monitor TTY mode output

11	4400		Monitor TTY mode control on.   (Set MONMOD)

12	5000		Monitor TTY mode control off.  (Clear MONMOD)

13	5400		Monitor TTY state
				Returns status of Monitor TTY mode (MONMOD)
				When MONMOD≠0 the main loop of KLDCP behaves
				differently.
				TTY input:
				$DTF11←character; $DTMTI←-1; 11 rings 10.
				TTY output (function 10) character is immediately
				sent to the CTY (which had better be ready).
				When the CTY output is finished, $DTMTD←-1;
				11 rings 10.

14	6000		unused.  use of these commands is a programming error
15	6400		unused.
16	7000		unused.
17	7400		unused.

KL10 UPT/EPT Special Locations

EPT

42-57	Standard Prioity interrupt locations

142	DTE0 Vector Interrupt Instruction
				;		BY THE 11 EVERY TICK)

421	Exec AROV Trap Instruction
422	Exec PDLOV Trap Instruction
423	Exec TRAP-3 Trap Instruction

444	DTE20 OPERATION COMPLETE FLAG
445		CLOCK INTERRUPT FLAG
447		TO 11 ARGUMENT
450		FROM 11 ARGUMENT
451		TO 11 COMMAND WORD
454		LAST KEY STRUCK ON CTY
455		MONITOR TTY OUTPUT DONE FLAG
456		MONITOR TTY INPUT READY FLAG
457		PDP-10 SWITCH REGISTER (DEPOSITED HERE)

510-511	Time base
512-513 Performance Analyis count
514	Interval Timer Vector Interrupt Instruction


UPT
421	User AROV Trap Instruction
422	User PDLOV Trap Instruction
423	User TRAP-3 Trap Instruction
424	MUUO stored here
425	MUUO old PC word
426	Process Context Word

430	Kernel     No Trap PC word
431	Kernel        Trap PC word
432	Supervisor No Trap PC word
433	Supervisor    Trap PC word
434	Concealed  No Trap PC word
435	Concealed     Trap PC word
436	Public     No Trap PC word
437	Public        Trap PC word

500	Page Fail Word
501	Page Fail Old PC
502	Page Fail New PC

504-505	EBOX meter word
506-507 MBOX meter word
Monitor Programming

UUOs from user mode will set Previous Context User (PCU = Bit 6 in PC)
and set current ac block = 0; previous ac block=1.

UUOs from kernal mode will clear PCU set current ac=0, previous=1.

Context switching:
When the map is changed, the previous context acs should be changed
too.  That is, contents of AC block 1 should be saved in old user's
shadow, and new contents of block 1 should be loaded from new user's
shadow.

All bare machine programs will have to be changed for the KL10.  Interfaces
to CTY, IOP, DC (and thus MTA, DTA) have been changed.

When taking an interrupt (by a JSR) some user mode PC flags are kept in the 
new (exec mode) PC. One of these is AR OV (bit 0) which regretably means
PCP (previous context public) in exec mode.  Therefore, on all interrupts
where user core will be referenced, PCP should be cleared in the exec mode
PC.

CONO PI,<Turn off selected channel> is not effective immediately.  This
means that all channel's interrupt code must test for the condition
of being in progress on a channel that's been turned off.  If that condition
is detected, and it isn't the case that this channel was GEN'ed on, then
the interrupt should be dismissed.

CONO PI,<generate interrupt on selected channel> has two peculiarities.
If the GEN is aimed at a higher priority channel then it isn't immediately
effective. In this case, the CONO PI,<GEN channel> should be followed by
a logical no-op that requires an EBUS cycle such as CONO PI,PION.
If the GEN is aimed at a lower priority channel then one should beware
the fact that the GEN isn't effective until after the present channel is
dismissed.  If it's necessary to get to a lower priority channel without
returing to the interrupted process then you must dismiss to an exec mode
loop or something.
	KL10 Folklore (from MIT)

Sometimes an MF10 memory gets hung.  Often the INC RQ light will be
on. Sometimes raising the RESET switch inside the memory's front door
will help; sometimes a module in the port control is fried.  (Any of
several modules.)

TU41 blower belt has to be the correct belt, has to not be worn out,
and has to have pulleys aligned.  Otherwise it drops off or breaks
and tape rotates backwards.

RP04 oscillating seeks & Maytag mode when loading => tachometer output
needs to be adjusted.

When powering machine back on, circuit breaker in disk DF10 may trip.

When powering machine back on, sometimes disk #0 needs to be stopped,
powered off and on, and started again, to reset the two-massbus
switch.

If DECtape motor doesn't win, may be G848 seating problem.

If kicking the LA36 causes power fail, "power warn" lead to top left
edge of CPU backplane needs to be disconnected.  (Apparently the other
end is unconnected.) [Missing ECO in 863.]

Bad door-open switches (?) in MF10.  Memories have to be operated with
over-ride turned on.

Apparently power supplies in CPU and IO box can drift voltages.

Apparently air-flow sensors can fail sporadically.  I am told that
disconnecting one => indication of good airflow.

RP04 attention/error conditions are super-random.

Often mysterious marginality is caused by bad seating of modules.

CONO'ing a PI channel off doesn't necessarily prevent it from
interrupting. It works to have each interrupt routine do CONSO to make
sure the channel is enabled, and dismiss if not.

Before running a memory diagnostic, do PE 0, because the memory
diagnostics don't know how to handle parity faults.

MF10's always fail solidly.

Obscure cases in the microcode tend to have bugs.  E.g.  you could
interrupt out of a PI cycle, hence BLKI/BLKO as interrupt instructions
tended to be flakey.

When running any diagnostic, even the 'DG' series, you better reload with old
	microcode (U.RAM).

When running DDDFA the channel has to be in KA mode.  This is a bug in the program.

User programming differences between the KL10 and the KA10.
Including some information pertaining to the 8.00 series operating
system.

							6/13/76 REG

Preliminary information.   For further details, consult REG or JBR.

AOBJN
KA10 adds 1,,1 to the AC.  The KL does the same, but suppresses the
carry out of bit 18.  That is, if AC contains X,,-1 then on the KA
the result of AOBJN is X+2,,0 and on the KL the result is X+1,,0.

Byte pointers
If the right half of a byte pointer is -1, the KA10 incrementing the
word address will produce a carry into the index field (the result of
an ILDB or IDPB in this circumstance is unpredictable).  On the KL10,
carry out of bit 18 is suppressed.

BLT
On the KA10 the AC of a BLT instruction is unpredictably changed by
the BLT.  On the KL10, before any data is moved, the quantity <last
source address+1>,,<last destination address+1> is stored in the BLT
AC.  If the BLT AC is stored by the BLT (i.e., as a destination) then
it ought to be the last destination location, otherwise, effects of
interrupts may clobber the BLT AC.

Processor identification
The following code will distinguish between a PDP-6, KA10, KI10 and KL10,
in case you need to make this distinction in some program:

	JFCL	17,.+1			;CLEAR ALL PC FLAGS
	JRST	.+1			;TEST FOR PC CHANGE FLAG
	JFCL	1,PDP6			;ONLY PDP-6 PROCESSOR HAS PC CHANGE FLAG
	MOVNI	AC,1			;TEST FOR CARRY OUT OF BIT 18 IN AOBJN
	AOBJN	AC,.+1
	JUMPN	AC,KA10			;KA10 CARRIES ACROSS HALFWORDS
	MOVEI	AC,0			;ON A 1 WORD BLT, THE KI10 WON'T
	BLT	AC,0			;CHANGE THE BLT AC.
	JUMPE	AC,KI10			;IF BLT AC IS STILL ZERO, THIS IS A KI
KL10:

JRST 3, which sometimes appears in spacewar modules, is illegal.
Instead, use JRST 2, and set 10000,,0 in the word being indirected
through.

CONSZ APR,40 and CONSO APR,40 to distinguish between processors
should NOT be used.  Instead, locations 326 (SKIPP1) and 327 (SKIPP2)
contain instructions, which when executed from a spacewar module,
will skip if executed on P1 or skip if executed on P2.  The
instructions should be read into your core image by a PEEK UUO or
somesuch executed at user level (prior to starting your spacewar
module).

The KA10 and PDP-6 FIX instruction, opcode 247 on the KA (and 120-127
and 247 on the PDP-6), does not exist in the KL10.  It will, however,
trap to the monitor which will simulate the effect of the old FIX
instruction.  This simulation may readily be expected to run 50 to
200 times slower than the KA10 version.  It's strongly recommended
that the new KL10 FIX instruction (mnemonic KIFIX in FAIL) be used
instead.  (KIFIX is different from KAFIX.  See below.)

The KA10 long mode floating point instructions (FADL, FSBL, FMPL,
FDVL) and two other floating point instructions UFA and DFN are not
implemented in our KL10's microcode.  These instructions will trap as
UUOs and be simulated by the monitor, running 50 to 200 times slower
than the KA10 versions.  If your program uses these to implement KA10
style double precision floating point, then you are strongly advised
to convert to KL10 hardware double precision format.

UUOs from spacewar mode on the KL10 will reference the spacewar level
accumulators (instead of the user mode accumulators).

Spacewar no longer runs PI in progress on PI channel 7.  Instead it
runs at user level (i.e., not PI in progress anywhere) and channel
7 activity is curtailed except for the spacewar timeout function.

Proprietors of programs that do disk I/O in buffered mode should
consider increasing the number of buffers.  Reasonable choices for
the number of buffers are 19, 10, 7, and 5.  In general, your program
will be able to process data 5 times faster, so that minimizing the
number of disk operations needed by you program will decrease its
overall running time (but not its CPU time) and decrease the disk
bottleneck.  There is no advantage to having more than 19 buffers per
channel.  If your program is largely compute bound, increasing the
buffer size won't help very much.  The disadvantage to having more
buffers is that it increases the total core requirement of the job.

KL10 New instructions: [Note that if you use these instructions, your
program can't be run on the KA10.  If we roll back, you get to
rewrite your program.  The safest thing to do is to wait until the
KL10 is solid, or write programs that figure out which CPU is up, and
execute only appropriate instructions.]

Adjust byte pointer
	IBP AC,E If the AC field of an IBP instruction is not zero,
then AC contains the number of times to increment the byte pointer
addressed by E.  The incremented byte pointer is returned in AC with
contents of E unchanged.  The "increment" may be negative.  NOTE:
This instruction does not always produce the same result as an
iterated IBP.  The difference is that the same byte alignment that is
present in C(E) is preserved by Adjust Byte pointer (if an IBP
crosses a word boundary the bytes become left adjusted in a word).

Example of the difference:
	MOVEI AC,1 		;(AC ≠ 0)
	IBP AC,[000700,,0] 	;result (in AC) is 340700,,1
				;000700 points to right adjusted
				;7 bit bytes as does 340700

	MOVE AC,[000700,,0]
	MOVEM AC,TEMP
	IBP TEMP		;result (in TEMP) is 350700,,1
				;350700 points to left adjusted bytes

ADJSP AC,E
	Adjust stack pointer.  E,,E is added to AC (carry out of bit
18 is suppressed).  If the sign of AC changes, a PDLOV trap results.
E may be negative.

Double precision integer arithmetic.  Operands are 70 bits and a sign
bit (bit 0 of low order word is ignored).  This is the same integer
format that is produced by MUL.

In the descriptions that follow, "AC+1", "AC+2", and "AC+3" are all meant
to be taken modulo 20 (octal).

DADD AC,E
		C(AC, AC+1) ← C(AC, AC+1) + C(E, E+1)

DSUB AC,E
		C(AC, AC+1) ← C(AC, AC+1) - C(E, E+1)

DMUL AC,E
		C(AC, AC+1, AC+2, AC+3) ← C(AC, AC+1) * C(E, E+1)

DDIV AC,E
		C(AC, AC+1)   ← Quotient  of C(AC, AC+1, AC+2, AC+3) / C(E, E+1)
		C(AC+2, AC+3) ← Remainder of C(AC, AC+1, AC+2, AC+3) / C(E, E+1)

EXTEND	
	USERS ARE ADVISED TO AVOID "EXTEND".
	Various conversion and string manipulation operations are
available.  Details will be forthcoming when we decide what subset of
the DEC EXTEND instruction to implement.  We're short on microcode
space so some of the DEC supplied EXTEND code may have to be
sacrificed.  The existing microcode for EXTEND has not been extensively
tested; it may be buggy, especially with respect to interrupts.

DMOVE AC,E
		C(AC, AC+1) ← C(E, E+1)

DMOVN AC,E
		C(AC, AC+1) ← -C(E, E+1)

DMOVEM AC,E
		C(E, E+1) ← C(AC, AC+1)

DMOVNM AC,E
		C(E, E+1) ← -C(AC, AC+1)

DFAD AC,E
		C(AC, AC+1) ← C(AC, AC+1) + C(E, E+1)

DFSB AC,E
		C(AC, AC+1) ← C(AC, AC+1) - C(E, E+1)

DFMP AC,E
		C(AC, AC+1) ← C(AC, AC+1) * C(E, E+1)

DFSB AC,E
		C(AC, AC+1) ← C(AC, AC+1) / C(E, E+1)

KIFIX AC,E
	AC ← contents of E (a floating point number) converted to integer format.
Truncation of the fraction moves the result closer to zero.  (E.g., 1.9 is
truncated to 1, -1.9 is truncated to -1).  (Fortran style IFIX)

FIXR AC,E
	AC ← contents of E (a floating point number) converted to integer format.
Fractional part is rounded by adding 0.5 and then truncating towards -∞.
(E.g., 1.5 is rounded to 2, -1.5 is rounded to -1, -1.6 is rounded to -2)
(Algol style real to integer conversion).

FLTR AC,E
	AC ← contents of E (an integer) converted (by rounding, if needed) to
floating point format.

KL10 PC flag bit assignments:

 0	AR OV
 1	AR CRY0						
 2	AR CRY1
 3	FOV
 4	FPD (First Part Done, essentially the same as BIS)
 5	User
 6	User In-Out
 7	Public  (Setting this bit causes a proprietary violation)
 8	Address Failure Inhibit
 9	Trap 2
10	Trap 1
11	FXU
12	DCK
13-17	Zero
18-35	PC

All bare machine programs will have to be changed for the KL10.
Interfaces to CTY, IOP, DC (and thus MTA, DTA) have been changed.
Any programs that reference these from IOT user mode or spacewar mode
are now incorrect.
Reloading the KL10

RELOADING:

0.  If there has been a power failure, go to 100.

1.  If a message such as "KL10 Halted .... " appears followed by
">." at the left margin go to step 3.  The important part is that
">." should appear to signify that KLDCP is listening.

2.  Type ↑X (i.e., control X).  The response should be "KLDCP" and a
crlf and a period.  You may sometimes have to wait a few seconds for
this response.  If you don't get a period or ">." at the left margin,
go to 100.

3.  Type "DS" and return.  If you get the response "DSKDMP" go to
step 4, otherwise, try "MR" and then "DS" (each terminated by
return).  If you don't get "DSKDMP" as a response to DS, then if
the KA10 is runing, stop it and repeat this step.   If you get
"DEPOSIT/EXAMINE ERROR IN DS" then perform step 103 and repeat step 3.
If the KA10 is stopped and DS doesn't get you "DSKDMP", go to 100.

4. Type "SYSTEM" and return to DSKDMP.  If the system reloads and
starts you are winning.  Otherwise, if the KA10 is running, stop it
and repeat steps 3 and 4.  If the KA10 is stopped and DSKDMP still
doesn't work, you need help.




********************************************

Don't come here unless directed by the steps above.

100.  Start the PDP-11 at 100014.  [Set 100014 in the PDP-11 switches,
press halt, then move halt back to it's upper position, press load address
then press start.]  If the console types "Stanford KL10 Diagnositic Console
Program" (or something like that) then you've got a KLDCP to talk to.  Go to
102.

101. Make sure a dectape labeled "KL10 bootstrap" is mounted on a PDP-11
dectape drive that is selected to unit 0 and is enabled for "remote"
(i.e., computer) operation.  Press "LOAD DECTAPE" [located above and to
the left of the red "Emergency Power Off" button] and hold it for
at least a slow count to one.  The dectape should spin and eventually
something like "TCDP monitor" should be typed.  Type in "KLDCP" and
return.  KLDCP should load and type a message - Go to 102.
If you don't get to "TCDP" you might try pressing the LOAD DECTAPE button
again.  If you get to TCDP and the "KLDCP" command doesn't work, call for
help.

102. If there's been a power failure you will have to reload the
KL10's microcode.  Type "LR SU" to KLDCP.  If any error messages are
printed, you need help.

103. [Only if there's been a power failure, or in other exceptional
circumstances] After loading the microcode, you must configure the
memory adapter.  One of the commands "I X1", "I X2", or "I X4" should
be used.  Currently "I X4" is right, and if that changes, this should
be changed too.

104. If the command DS doesn't work, then load DSKDMP boot into the PDP-11
by "LD BOOT"

105. You should now be able to perform steps 3 and 4, but if that doesn't
work, you need help.

Help:	REG (9) 326-5879
	JBR (9) 494-3597